期刊簡介預(yù)計(jì)審稿時(shí)間： 12周，或約稿

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.

IEEE 計(jì)算機(jī)體系結(jié)構(gòu)快報(bào)是一個(gè)經(jīng)過嚴(yán)格同行評審的論壇，用于發(fā)布單處理器和多處理器計(jì)算機(jī)系統(tǒng)、計(jì)算機(jī)體系結(jié)構(gòu)、微體系結(jié)構(gòu)、工作負(fù)載特性、性能評估和模擬技術(shù)以及功耗感知計(jì)算等領(lǐng)域的早期高影響力成果。歡迎提交有關(guān)計(jì)算機(jī)體系結(jié)構(gòu)的任何主題的論文，特別是（但不限于）：微處理器和多處理器系統(tǒng)、微體系結(jié)構(gòu)和 ILP 處理器、工作負(fù)載特性、性能評估和模擬技術(shù)、編譯器硬件和操作系統(tǒng)硬件交互、互連體系結(jié)構(gòu)、內(nèi)存和緩存系統(tǒng)、體系結(jié)構(gòu)級別的功耗和散熱問題、I/O 體系結(jié)構(gòu)和技術(shù)、對先前發(fā)布結(jié)果的獨(dú)立驗(yàn)證、對不成功技術(shù)的分析、特定領(lǐng)域的處理器體系結(jié)構(gòu)（例如嵌入式、圖形、網(wǎng)絡(luò)等）、實(shí)時(shí)和高可用性體系結(jié)構(gòu)、可重構(gòu)系統(tǒng)。

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