期刊簡介預(yù)計審稿時間： 12周，或約稿

The focus of this journal is on formal methods for designing, implementing, and validating the correctness of hardware (VLSI) and software systems. The stimulus for starting a journal with this goal came from both academia and industry. In both areas, interest in the use of formal methods has increased rapidly during the past few years. The enormous cost and time required to validate new designs has led to the realization that more powerful techniques must be developed. A number of techniques and tools are currently being devised for improving the reliability, and robustness of complex hardware and software systems. While the boundary between the (sub)components of a system that are cast in hardware, firmware, or software continues to blur, the relevant design disciplines and formal methods are maturing rapidly. Consequently, an important (and useful) collection of commonly applicable formal methods are expected to emerge that will strongly influence future design environments and design methods.

本期刊的重點是設(shè)計、實施和驗證硬件（VLSI）和軟件系統(tǒng)正確性的形式化方法。以此為目標(biāo)創(chuàng)辦期刊的動機(jī)來自學(xué)術(shù)界和工業(yè)界。在這兩個領(lǐng)域，人們對使用形式化方法的興趣在過去幾年中迅速增加。驗證新設(shè)計所需的巨大成本和時間使人們意識到必須開發(fā)更強(qiáng)大的技術(shù)。目前正在設(shè)計許多技術(shù)和工具來提高復(fù)雜硬件和軟件系統(tǒng)的可靠性和穩(wěn)健性。雖然系統(tǒng)中硬件、固件或軟件的（子）組件之間的界限繼續(xù)模糊，但相關(guān)的設(shè)計學(xué)科和形式化方法正在迅速成熟。因此，預(yù)計將出現(xiàn)一個重要（且有用）的常用形式化方法集合，這將對未來的設(shè)計環(huán)境和設(shè)計方法產(chǎn)生重大影響。

《Formal Methods In System Design》(系統(tǒng)設(shè)計中的形式化方法)編輯部通訊方式為SPRINGER, VAN GODEWIJCKSTRAAT 30, DORDRECHT, NETHERLANDS, 3311 GZ。如果您需要協(xié)助投稿或潤稿服務(wù)，您可以咨詢我們的客服老師。我們專注于期刊咨詢服務(wù)十年，熟悉發(fā)表政策，可為您提供一對一投稿指導(dǎo)，避免您在投稿時頻繁碰壁，節(jié)省您的寶貴時間，有效提升發(fā)表機(jī)率，確保SCI檢索（檢索不了全額退款）。我們視信譽(yù)為生命，多方面確保文章安全保密，在任何情況下都不會泄露您的個人信息或稿件內(nèi)容。